this has a fairly in-depth decode of x86 cpu features, sample below.

ok to import?

(afaik we don't have a way to bind threads to cores so it's very hit
and miss if you're trying to get details from a core which doesn't
end up scheduled very often).

----
"cpuid" dumps results from the x86 CPUID instruction, and decodes
information from certain leaves.

NOTE: the code in this software to bind to a specific CPU is non functional
on OpenBSD; if you are trying to find information from different cores, you'll
need to run it multiple times until the process is scheduled on the core of
interest.
----

----
CPU 0:
Maximum basic CPUID leaf: 0x00000020

CPU vendor string: 'GenuineIntel'

Signature:  0x000906a3
  Family:   0x06 (6)
  Model:    0x9a (154)
  Stepping: 0x03 (3)

Local APIC: 0
Maximum number of APIC IDs per package: 64
CLFLUSH size: 64
Brand ID: 0

Base features, edx:
  x87 FPU on chip
  virtual-8086 mode enhancement
  debugging extensions
  page size extensions
  time stamp counter
  RDMSR and WRMSR support
  physical address extensions
  machine check exception
  CMPXCHG8B instruction
  APIC on chip
  SYSENTER and SYSEXIT instructions
  memory type range registers
  PTE global bit
  machine check architecture
  conditional move instruction
  page attribute table
  36-bit page size extension
  CLFLUSH instruction
  debug store
  ACPI
  MMX instruction set
  FXSAVE/FXRSTOR instructions
  SSE instructions
  SSE2 instructions
  self snoop
  max APIC IDs reserved field is valid
  thermal monitor
  pending break enable
Base features, ecx:
  SSE3 instructions
  PCLMULQDQ instruction
  64-bit DS area
  MONITOR/MWAIT instructions
  CPL qualified debug store
  virtual machine extensions
  safer mode extensions
  Enhanced Intel SpeedStep
  thermal monitor 2
  SSSE3 instructions
  silicon debug
  fused multiply-add AVX instructions
  CMPXCHG16B instruction
  xTPR update control
  perfmon and debug capability
  process-context identifiers
  SSE4.1 instructions
  SSE4.2 instructions
  x2APIC
  MOVBE instruction
  POPCNT instruction
  TSC deadline
  AES instructions
  XSAVE/XRSTOR instructions
  OS-enabled XSAVE/XRSTOR
  AVX instructions
  16-bit FP conversion instructions
  RDRAND instruction

Cache descriptors:
  [NOTICE] For cache data, see Deterministic Cache Parameters leaf instead
  [NOTICE] For TLB data, see Deterministic Address Translation leaf instead
  64-byte prefetching

Processor serial number: disabled (or not supported)

Deterministic Cache Parameters:
   48KB L1 data cache
        12-way set associative
        64 byte line size
        Self-initializing
        Shared by max 2 threads

   32KB L1 code cache
        8-way set associative
        64 byte line size
        Self-initializing
        Shared by max 2 threads

    1MB L2 unified cache
        10-way set associative
        64 byte line size
        Self-initializing
        Shared by max 8 threads

   18MB L3 unified cache
        12-way set associative
        64 byte line size
        Self-initializing
        Complex indexing
        Shared by max 64 threads

MONITOR/MWAIT features:
  Smallest monitor-line size: 64 bytes
  Largest monitor-line size: 64 bytes
  Interrupts as break-event for MWAIT, even when interrupts off
  C1 sub C-states supported by MWAIT: 2
  C3 sub C-states supported by MWAIT: 2
  C5 sub C-states supported by MWAIT: 1
  C7 sub C-states supported by MWAIT: 1

Intel Thermal and Power Management Features:
  Digital temperature sensor
  Intel Turbo Boost Technology
  Always running APIC timer (ARAT)
  Power limit notification controls
  Clock modulation duty cycle extensions
  Package thermal management
  Hardware-managed P-state base support (HWP)
  HWP notification interrupt enable MSR
  HWP activity window MSR
  HWP energy/performance preference MSR
  HWP package level request MSR
  HWP Capabilities, Highest Performance change
  HWP PECI override
  Flexible HWP
  Fast access mode for IA32_HWP_REQUEST MSR
  Hardware feedback MSRs
  Ignoring Idle Logical Processor HWP request
  HWP control MSR
  Enhanced hardware feedback MSRs
  Hardware Coordination Feedback Capability (APERF and MPERF)
  Performance-energy bias preference
  Interrupt thresholds in DTS: 2

Structured extended feature flags (ecx=0), ebx:
  FSGSBASE instructions
  IA32_TSC_ADJUST MSR supported
  Bit Manipulation Instructions (BMI1)
  Advanced Vector Extensions 2.0 (AVX2)
  x87 FPU data pointer updated only on x87 exceptions
  Supervisor Mode Execution Protection (SMEP)
  Bit Manipulation Instructions 2 (BMI2)
  Enhanced REP MOVSB/STOSB
  INVPCID instruction
  x87 FPU CS and DS deprecated
  RDSEED instruction
  Multi-Precision Add-Carry Instruction Extensions (ADX)
  Supervisor Mode Access Prevention (SMAP)
  CLFLUSHOPT instruction
  cache line write-back instruction (CLWB)
  Intel Processor Trace
  SHA-1/SHA-256 instructions
Structured extended feature flags (ecx=0), ecx:
  User Mode Instruction Prevention (UMIP)
  Protection Keys for User-mode pages (PKU)
  OS has enabled protection keys (OSPKE)
  Wait and Pause Enhancements (WAITPKG)
  CET shadow stack (CET_SS)
  Galois Field NI / Galois Field Affine Transformation (GFNI)
  VEX-encoded AES-NI (VAES)
  VEX-encoded PCLMUL (VPCL)
  Total Memory Encryption (TME_EN)
  Read Processor ID (RDPID)
  Key locker (KL)
  32-bit Direct Stores (MOVDIRI)
  64-bit Direct Stores (MOVDIRI64B)
  Protection keys for supervisor-mode pages (PKS)
Structured extended feature flags (ecx=0), edx:
  Fast Short REP MOV
  MD_CLEAR
  SERIALIZE
  Hybrid
  PCONFIG
  Architectural LBRs
  CET indirect branch tracking (CET_IBT)
  Speculation Control (IBRS and IBPB)
  Single Thread Indirect Branch Predictors (STIBP)
  L1 Data Cache (L1D) Flush
  IA32_ARCH_CAPABILITIES MSR
  IA32_CORE_CAPABILITIES MSR
  Speculative Store Bypass Disable (SSBD)

Structured extended feature flags (ecx=1), eax:
  AVX Vector Neural Network Instructions (AVX-VNNI)
  Fast short STOSB
  History reset (HRESET)
Unaccounted for in 0x00000007:0x00000001:
  eax:0x00000000 ebx:0x00000000 ecx:0x00000000 edx:0x00040000

Structured extended feature flags (ecx=2), edx:
  Fast store forwarding disable without spec store bypass (PSFD)
  IPRED control
  RRSBA control
  BHI control
  MONITOR/UMONITOR unaffected by overflow

Architectural Performance Monitoring
  Version: 5
  Counters per logical processor: 6
  Counter bit width: 48
  Number of contiguous fixed-function counters: 3
  Bit width of fixed-function counters: 48
  AnyThread deprecated
  Supported performance counters:
    Core cycles
    Instructions retired
    Reference cycles
    Last-level cache reference
    Last-level cache miss
    Branches retired
    Branches mispredicted
    Top-down slots event

x2APIC Processor Topology:
  Inferred information:
    Logical total:       12 (?)
    Logical per socket:  16
    Cores per socket:    8
    Threads per core:    2

  x2APIC ID 0 (socket 0, core 0, thread 0)

Extended State Enumeration
  Valid bit fields for lower 32 bits of XCR0:
    0 - Legacy x87
    1 - 128-bit SSE
    2 - 256-bit AVX YMM_Hi128
    9 - Protected keys

  Valid bit fields for upper 32-bits of XCR0:
    0x00000000

  Maximum size required for all enabled features:   832 bytes

  Maximum size required for all supported features: 2696 bytes

  Size of XSAVE area containing all enabled states: 848
  Features available:
    0 - XSAVEOPT
    1 - XSAVEC and compacted XRSTOR
    2 - XGETBV with ECX=1
    3 - XSAVES/XRSTORS and IA32_XSS

  Extended state for 256-bit AVX YMM_Hi128 requires 256 bytes, offset 576

Processor Trace Enumeration
  CR3 filtering
  Configurable PSB, Cycle-Accurate Mode
  Filtering preserved across warm reset
  MTC timing packet, suppression of COFI-based packets
  PTWRITE
  PSB and PMI preservation MSRs
  ToPA output scheme
  ToPA tables hold multiple output entries
  Single-range output scheme

  Number of configurable address ranges for filtering: 2
  Supported MTC period encodings: 0x0249
  Supported cycle threshold value encodings: 0x003f
  Supported configurable PSB frequency encodings: 0x003f

Time Stamp Counter and Core Crystal Clock Information
  Core crystal clock: 38400000 Hz
  TSC to core crystal clock ratio: 130 / 2
  TSC frequency: 2496000 kHz

Processor Frequency Information
  Base frequency: 2500 MHz
  Maximum frequency: 4800 MHz
  Bus (reference) frequency: 100 MHz

Deterministic Address Translation Parameters:
        L1 Code TLB: 4KB pages
                     8-way set associative
                     32 entries
                     Shared by max 2 threads

        L1 Code TLB: 2MB or 4MB pages
                     8-way set associative
                     4 entries
                     Shared by max 2 threads

  L1 Store-only TLB: 4KB, 2MB, 4MB or 1GB pages
                     fully associative
                     Shared by max 2 threads

   L1 Load-only TLB: 4KB pages
                     4-way set associative
                     Shared by max 2 threads

   L1 Load-only TLB: 2MB or 4MB pages
                     4-way set associative
                     Shared by max 2 threads

   L1 Load-only TLB: 1GB pages
                     fully associative
                     Shared by max 2 threads

      L2 Shared TLB: 4KB, 2MB or 4MB pages
                     8-way set associative
                     128 entries
                     Shared by max 2 threads

      L2 Shared TLB: 4KB or 1GB pages
                     8-way set associative
                     128 entries
                     Shared by max 2 threads

Maximum extended CPUID leaf: 0x80000008

Extended features, edx:
  SYSENTER and SYSEXIT instructions
  XD bit
  1GB page support
  RDTSCP instruction
  long mode (EM64T)
Extended features, ecx:
  LAHF/SAHF supported in 64-bit mode
  LZCNT instruction
  3DNow! prefetch instructions

Processor Name: 12th Gen Intel(R) Core(TM) i7-1270P

Advanced Power Management features, edx:
  Invariant TSC

Physical address size: 46 bits
Linear address size: 48 bits
----