Index | Thread | Search

From:
Thomas Dettbarn <dettus@dettus.net>
Subject:
Three ports incoming: cad/prjpeppercorn, cad/nextpnr, cad/openfpgaloader (Please review)
To:
ports@openbsd.org
Date:
Tue, 9 Jun 2026 00:48:44 +0200

Download raw body.

Thread
  • Thomas Dettbarn:

    Three ports incoming: cad/prjpeppercorn, cad/nextpnr, cad/openfpgaloader (Please review)

Hello!

Recently, I found out that designing FPGAs on OpenBSD is possible, using
the following tools: Yosys, nextpnr and openFPGALoader. I have thus taken
the liberty of creating three ports:

cad/prjpeppercorn (a dependency for cad/nextpnr)
cad/nextpnr
cad/openfpgaloader

I will send them in three separate emails, it would be wonderful if you
allow them to become part of the ports tree.


I do need some help from more experienced porters, please have a look
and tell me what I can do to improve their standards.


Some notes about the ports:
- For cad/prjpeppercorn, I was able to use release tag 1.13. It required one
small patch, however. The other two are using the latest commits, I plan
on using tags when they become available. The latest tag required too many
patches for both of them.
- For cad/nextpnr, a larger-than-default amount of RAM is required for the
build. I added a note in the Makefile. (We are talking about 16384M)
- Even though cad/openfpgaloader compiles out of the repo, it requires the
KERNEL TO BE PATCHED (for certain devices). I have already raised this
issue on misc@ a couple of days ago. But since this is a very specific
problem, only happening to very specific persons, I opted to add a note
to pkg/DESCR.


About the version numbers:
For the version number, I opted to add an "a" to the latest tag, hence the
line V=1.1.1a in the Makefile of the openfpgaloader.
The REVISION is currently set to 0.



One more probem:
There is already a port for cad/yosys. However, this port seems to be
unmaintained since 2021. I have already tried to contact the maintainer
via email already. Unfortunately, the email seems to be unmaintained as
well. My first impulse would now be to create a new port, using his work
as blueprint. Is that a good idea?



Now, my questions to you are:

1. What can I do to improve the quality/formatting of the ports?
2. What should I do about the larger-than-default amount of RAM?
3. Any suggestions regarding the kernel patch?
4. How should I proceed with the outdated cad/yosys port?
5. Is my Version/Revision numbering scheme correct?



Thomas