Mailing List Archive | ports@openbsd.org

Please find new port cad/yosys-takeover(*) attached to this email. (In the form of a git diff). (*) IN WOULD LIKE TO ASK YOU FOR A HUGE FAVOR and giving it a better name, before you add it to the ports tree. There is already a project with the name cad/yosys inside the ports tree. My first idea was to patch/replace it, since it is the same software, albeit ported 5 years ago. HOWEVER, as Michael pointed out in his email https://marc.info/?l=openbsd-ports&m=178129507665335&w=2 there is one more port which adds cad/yosys as dependency: cad/qflow. I do not feel comfortable with replacing/patching/updating that port as well, and not comfortable depriving users of said port with a working version. Hence the new name cad/yosys-takeover, BUT I DO NOT LIKE IT. About this port: Thus far, the only thing I can say with confidence is that ItWorksOnMyMachine(tm). In total, I plan on sending four ports over this email list: cad/prjpeppercorn-1.13 cad/nextpnr-0.10pl20260613 cad/openfpgaloader-1.1.1pl20260604 cad/yosys-takeover-0.66pl20260612 ... this one needs a better name. (See its accompanying email for details). In lieu of a proper method of checking, I have set up a website with a simple helloworld style example: https://dettus.net/fpga_stuff/1.html. Even if you do not have a physical FPGA board at home, the instructions might give you an idea about how the tools are supposed to work together. So, please have another review. Thank you so so much! Please have a look into this packages README file as well. Running it will require more RAM than the default user is granted by /etc/login.conf(5). diff --git a/cad/yosys-takeover/Makefile b/cad/yosys-takeover/Makefile new file mode 100644 index 00000000000..42d8618aad5 --- /dev/null +++ b/cad/yosys-takeover/Makefile @@ -0,0 +1,30 @@ +COMMENT= Yosys Open SYnthesis Suite +CATEGORIES= cad +V= 0.66pl20260612 +DISTNAME= yosys-takeover-${V} + +GH_ACCOUNT= YosysHQ +GH_PROJECT= yosys +GH_COMMIT= 05805e8b93cc3b92a293c83c25fa3a93d54498d7 + + +DIST_TUPLE+= github jarro2783 cxxopts v3.2.1 libs/cxxopts/ +DIST_TUPLE+= github YosysHQ abc v0.65 abc/ + +HOMEPAGE= https://github.com/YosysHQ +MAINTAINER= Thomas Dettbarn <dettus@dettus.net> + +# ISC license +PERMIT_PACKAGE= Yes + +WANTLIB= c c++ c++abi m pthread z + +MODULES= devel/cmake +MODULES+= lang/python +NO_TEST= Yes + +LIB_DEPENDS= devel/libffi +BUILD_DEPENDS= devel/bison + +.include <bsd.port.mk> + diff --git a/cad/yosys-takeover/distinfo b/cad/yosys-takeover/distinfo new file mode 100644 index 00000000000..6a0a8610276 --- /dev/null +++ b/cad/yosys-takeover/distinfo @@ -0,0 +1,6 @@ +SHA256 (YosysHQ-abc-v0.65.tar.gz) = JD9SmxFVv3nNnq21DoJadG/1lfvKaGinS6I1iDKTyNk= +SHA256 (jarro2783-cxxopts-v3.2.1.tar.gz) = hB9J8uBFucY2WZfCqPv3bm8hUELdpFEaW7BLxevH+Io= +SHA256 (yosys-takeover-0.66pl20260612-05805e8b.tar.gz) = OKsb9APu2QnWRSTIXyBhijQosdMfLn0c997roA+qVMc= +SIZE (YosysHQ-abc-v0.65.tar.gz) = 7387477 +SIZE (jarro2783-cxxopts-v3.2.1.tar.gz) = 160606 +SIZE (yosys-takeover-0.66pl20260612-05805e8b.tar.gz) = 3667770 diff --git a/cad/yosys-takeover/patches/patch-CMakeLists_txt b/cad/yosys-takeover/patches/patch-CMakeLists_txt new file mode 100644 index 00000000000..d8886a1eda8 --- /dev/null +++ b/cad/yosys-takeover/patches/patch-CMakeLists_txt @@ -0,0 +1,13 @@ +Build check failed because of wrong flex version number. +Index: CMakeLists.txt +--- CMakeLists.txt.orig ++++ CMakeLists.txt +@@ -172,7 +172,7 @@ if (APPLE) + use_homebrew() + endif() + +-find_package(FLEX 2.6) ++find_package(FLEX 2.5.39) + set_package_properties(FLEX PROPERTIES + URL "https://github.com/westes/flex" + DESCRIPTION "The Fast Lexical Analyzer" diff --git a/cad/yosys-takeover/patches/patch-cmake_FindBISON_cmake b/cad/yosys-takeover/patches/patch-cmake_FindBISON_cmake new file mode 100644 index 00000000000..f0e46bba943 --- /dev/null +++ b/cad/yosys-takeover/patches/patch-cmake_FindBISON_cmake @@ -0,0 +1,13 @@ +The resulting environment variable was broken +Index: cmake/FindBISON.cmake +--- cmake/FindBISON.cmake.orig ++++ cmake/FindBISON.cmake +@@ -315,7 +315,7 @@ if(BISON_EXECUTABLE) + unset(_BISON_CMP0088) + + add_custom_command(OUTPUT ${BISON_TARGET_outputs} +- COMMAND ${CMAKE_COMMAND} -E env "M4=${BISON_M4_EXECUTABLE}" ++ COMMAND ${CMAKE_COMMAND} -E env + ${BISON_EXECUTABLE} ${BISON_TARGET_cmdopt} -o ${BisonOutput} ${_BisonInput} + VERBATIM + DEPENDS ${_BisonInput} diff --git a/cad/yosys-takeover/pkg/DESCR b/cad/yosys-takeover/pkg/DESCR new file mode 100644 index 00000000000..f5cf4b125f0 --- /dev/null +++ b/cad/yosys-takeover/pkg/DESCR @@ -0,0 +1,15 @@ +This is a framework for RTL synthesis tools. It currently has extensive +Verilog-2005 support and provides a basic set of synthesis algorithms for +various application domains. + +Yosys can be adapted to perform any synthesis job by combining the existing +passes (algorithms) using synthesis scripts and adding additional passes as +needed by extending the yosys C++ code base. + +Yosys is free software licensed under the ISC license (a GPL compatible +license that is similar in terms to the MIT license or the 2-clause BSD +license). + +Third-party software distributed alongside this software is licensed under +compatible licenses. Please refer to abc and libs subdirectories for their +license terms. diff --git a/cad/yosys-takeover/pkg/PLIST b/cad/yosys-takeover/pkg/PLIST new file mode 100644 index 00000000000..1d750bb7926 --- /dev/null +++ b/cad/yosys-takeover/pkg/PLIST @@ -0,0 +1,395 @@ +@bin bin/yosys +@bin bin/yosys-abc +bin/yosys-config +@bin bin/yosys-filterlib +bin/yosys-smtbmc +bin/yosys-witness +share/doc/pkg-readmes/${PKGSTEM} +share/yosys/ +share/yosys/abc9_map.v +share/yosys/abc9_model.v +share/yosys/abc9_unmap.v +share/yosys/achronix/ +share/yosys/achronix/speedster22i/ +share/yosys/achronix/speedster22i/cells_map.v +share/yosys/achronix/speedster22i/cells_sim.v +share/yosys/adff2dff.v +share/yosys/analogdevices/ +share/yosys/analogdevices/abc9_model.v +share/yosys/analogdevices/arith_map.v +share/yosys/analogdevices/brams.txt +share/yosys/analogdevices/brams_defs.vh +share/yosys/analogdevices/brams_map.v +share/yosys/analogdevices/cells_map.v +share/yosys/analogdevices/cells_sim.v +share/yosys/analogdevices/dsp_map.v +share/yosys/analogdevices/ff_map.v +share/yosys/analogdevices/lut_map.v +share/yosys/analogdevices/lutrams.txt +share/yosys/analogdevices/lutrams_map.v +share/yosys/analogdevices/mux_map.v +share/yosys/anlogic/ +share/yosys/anlogic/arith_map.v +share/yosys/anlogic/brams.txt +share/yosys/anlogic/brams_map.v +share/yosys/anlogic/cells_map.v +share/yosys/anlogic/cells_sim.v +share/yosys/anlogic/eagle_bb.v +share/yosys/anlogic/lutrams.txt +share/yosys/anlogic/lutrams_map.v +share/yosys/choices/ +share/yosys/choices/han-carlson.v +share/yosys/choices/kogge-stone.v +share/yosys/choices/sklansky.v +share/yosys/cmp2lcu.v +share/yosys/cmp2lut.v +share/yosys/cmp2softlogic.v +share/yosys/coolrunner2/ +share/yosys/coolrunner2/cells_counter_map.v +share/yosys/coolrunner2/cells_latch.v +share/yosys/coolrunner2/cells_sim.v +share/yosys/coolrunner2/tff_extract.v +share/yosys/coolrunner2/xc2_dff.lib +share/yosys/dff2ff.v +share/yosys/ecp5/ +share/yosys/ecp5/ccu2c_sim.vh +share/yosys/ecp5/cells_bb.v +share/yosys/ecp5/cells_ff.vh +share/yosys/ecp5/cells_io.vh +share/yosys/ecp5/cells_sim.v +share/yosys/ecp5/common_sim.vh +share/yosys/efinix/ +share/yosys/efinix/arith_map.v +share/yosys/efinix/brams.txt +share/yosys/efinix/brams_map.v +share/yosys/efinix/cells_map.v +share/yosys/efinix/cells_sim.v +share/yosys/efinix/gbuf_map.v +share/yosys/fabulous/ +share/yosys/fabulous/arith_map.v +share/yosys/fabulous/cells_map.v +share/yosys/fabulous/ff_map.v +share/yosys/fabulous/io_map.v +share/yosys/fabulous/latches_map.v +share/yosys/fabulous/prims.v +share/yosys/fabulous/ram_regfile.txt +share/yosys/fabulous/regfile_map.v +share/yosys/gate2lut.v +share/yosys/gatemate/ +share/yosys/gatemate/arith_map.v +share/yosys/gatemate/brams.txt +share/yosys/gatemate/brams_init_20.vh +share/yosys/gatemate/brams_init_40.vh +share/yosys/gatemate/brams_map.v +share/yosys/gatemate/cells_bb.v +share/yosys/gatemate/cells_sim.v +share/yosys/gatemate/inv_map.v +share/yosys/gatemate/lut_map.v +share/yosys/gatemate/lut_tree_cells.genlib +share/yosys/gatemate/lut_tree_map.v +share/yosys/gatemate/mul_map.v +share/yosys/gatemate/mux_map.v +share/yosys/gatemate/reg_map.v +share/yosys/gowin/ +share/yosys/gowin/arith_map.v +share/yosys/gowin/brams.txt +share/yosys/gowin/brams_map.v +share/yosys/gowin/brams_map_gw5a.v +share/yosys/gowin/cells_latch.v +share/yosys/gowin/cells_map.v +share/yosys/gowin/cells_sim.v +share/yosys/gowin/cells_xtra_gw1n.v +share/yosys/gowin/cells_xtra_gw2a.v +share/yosys/gowin/cells_xtra_gw5a.v +share/yosys/gowin/dsp_map.v +share/yosys/gowin/lutrams.txt +share/yosys/gowin/lutrams_map.v +share/yosys/greenpak4/ +share/yosys/greenpak4/cells_blackbox.v +share/yosys/greenpak4/cells_latch.v +share/yosys/greenpak4/cells_map.v +share/yosys/greenpak4/cells_sim.v +share/yosys/greenpak4/cells_sim_ams.v +share/yosys/greenpak4/cells_sim_digital.v +share/yosys/greenpak4/cells_sim_wip.v +share/yosys/greenpak4/gp_dff.lib +share/yosys/ice40/ +share/yosys/ice40/abc9_model.v +share/yosys/ice40/arith_map.v +share/yosys/ice40/brams.txt +share/yosys/ice40/brams_map.v +share/yosys/ice40/cells_map.v +share/yosys/ice40/cells_sim.v +share/yosys/ice40/dsp_map.v +share/yosys/ice40/ff_map.v +share/yosys/ice40/latches_map.v +share/yosys/ice40/spram.txt +share/yosys/ice40/spram_map.v +share/yosys/include/ +share/yosys/include/backends/ +share/yosys/include/backends/cxxrtl/ +share/yosys/include/backends/cxxrtl/runtime/ +share/yosys/include/backends/cxxrtl/runtime/README.txt +share/yosys/include/backends/cxxrtl/runtime/cxxrtl/ +share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/ +share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc +share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h +share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc +share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h +share/yosys/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h +share/yosys/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h +share/yosys/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_time.h +share/yosys/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h +share/yosys/include/backends/rtlil/ +share/yosys/include/backends/rtlil/rtlil_backend.h +share/yosys/include/frontends/ +share/yosys/include/frontends/blif/ +share/yosys/include/frontends/blif/blifparse.h +share/yosys/include/kernel/ +share/yosys/include/kernel/binding.h +share/yosys/include/kernel/bitpattern.h +share/yosys/include/kernel/cellaigs.h +share/yosys/include/kernel/celledges.h +share/yosys/include/kernel/celltypes.h +share/yosys/include/kernel/consteval.h +share/yosys/include/kernel/constids.inc +share/yosys/include/kernel/cost.h +share/yosys/include/kernel/drivertools.h +share/yosys/include/kernel/ff.h +share/yosys/include/kernel/ffinit.h +share/yosys/include/kernel/ffmerge.h +share/yosys/include/kernel/fmt.h +share/yosys/include/kernel/fstdata.h +share/yosys/include/kernel/gzip.h +share/yosys/include/kernel/hashlib.h +share/yosys/include/kernel/io.h +share/yosys/include/kernel/json.h +share/yosys/include/kernel/log.h +share/yosys/include/kernel/macc.h +share/yosys/include/kernel/mem.h +share/yosys/include/kernel/modtools.h +share/yosys/include/kernel/newcelltypes.h +share/yosys/include/kernel/qcsat.h +share/yosys/include/kernel/register.h +share/yosys/include/kernel/rtlil.h +share/yosys/include/kernel/satgen.h +share/yosys/include/kernel/scopeinfo.h +share/yosys/include/kernel/sexpr.h +share/yosys/include/kernel/sigtools.h +share/yosys/include/kernel/threading.h +share/yosys/include/kernel/timinginfo.h +share/yosys/include/kernel/utils.h +share/yosys/include/kernel/yosys.h +share/yosys/include/kernel/yosys_common.h +share/yosys/include/kernel/yosys_config.h +share/yosys/include/kernel/yw.h +share/yosys/include/libs/ +share/yosys/include/libs/ezsat/ +share/yosys/include/libs/ezsat/ezcmdline.h +share/yosys/include/libs/ezsat/ezminisat.h +share/yosys/include/libs/ezsat/ezsat.h +share/yosys/include/libs/fst/ +share/yosys/include/libs/fst/fstapi.h +share/yosys/include/libs/json11/ +share/yosys/include/libs/json11/json11.hpp +share/yosys/include/libs/sha1/ +share/yosys/include/libs/sha1/sha1.h +share/yosys/include/passes/ +share/yosys/include/passes/fsm/ +share/yosys/include/passes/fsm/fsmdata.h +share/yosys/include/passes/techmap/ +share/yosys/include/passes/techmap/libparse.h +share/yosys/intel/ +share/yosys/intel/common/ +share/yosys/intel/common/altpll_bb.v +share/yosys/intel/common/brams_m9k.txt +share/yosys/intel/common/brams_map_m9k.v +share/yosys/intel/common/ff_map.v +share/yosys/intel/common/m9k_bb.v +share/yosys/intel/cyclone10lp/ +share/yosys/intel/cyclone10lp/cells_map.v +share/yosys/intel/cyclone10lp/cells_sim.v +share/yosys/intel/cycloneiv/ +share/yosys/intel/cycloneiv/cells_map.v +share/yosys/intel/cycloneiv/cells_sim.v +share/yosys/intel/cycloneive/ +share/yosys/intel/cycloneive/cells_map.v +share/yosys/intel/cycloneive/cells_sim.v +share/yosys/intel/max10/ +share/yosys/intel/max10/cells_map.v +share/yosys/intel/max10/cells_sim.v +share/yosys/intel_alm/ +share/yosys/intel_alm/common/ +share/yosys/intel_alm/common/abc9_map.v +share/yosys/intel_alm/common/abc9_model.v +share/yosys/intel_alm/common/abc9_unmap.v +share/yosys/intel_alm/common/alm_map.v +share/yosys/intel_alm/common/alm_sim.v +share/yosys/intel_alm/common/arith_alm_map.v +share/yosys/intel_alm/common/bram_m10k.txt +share/yosys/intel_alm/common/bram_m10k_map.v +share/yosys/intel_alm/common/dff_map.v +share/yosys/intel_alm/common/dff_sim.v +share/yosys/intel_alm/common/dsp_map.v +share/yosys/intel_alm/common/dsp_sim.v +share/yosys/intel_alm/common/lutram_mlab.txt +share/yosys/intel_alm/common/megafunction_bb.v +share/yosys/intel_alm/common/mem_sim.v +share/yosys/intel_alm/common/misc_sim.v +share/yosys/intel_alm/cyclonev/ +share/yosys/intel_alm/cyclonev/cells_sim.v +share/yosys/lattice/ +share/yosys/lattice/arith_map_ccu2c.v +share/yosys/lattice/arith_map_ccu2d.v +share/yosys/lattice/arith_map_nexus.v +share/yosys/lattice/brams_16kd.txt +share/yosys/lattice/brams_8kc.txt +share/yosys/lattice/brams_map_16kd.v +share/yosys/lattice/brams_map_8kc.v +share/yosys/lattice/brams_map_nexus.v +share/yosys/lattice/brams_nexus.txt +share/yosys/lattice/ccu2c_sim.vh +share/yosys/lattice/ccu2d_sim.vh +share/yosys/lattice/cells_bb_ecp5.v +share/yosys/lattice/cells_bb_nexus.v +share/yosys/lattice/cells_bb_xo2.v +share/yosys/lattice/cells_bb_xo3.v +share/yosys/lattice/cells_bb_xo3d.v +share/yosys/lattice/cells_ff.vh +share/yosys/lattice/cells_io.vh +share/yosys/lattice/cells_map_nexus.v +share/yosys/lattice/cells_map_trellis.v +share/yosys/lattice/cells_sim_ecp5.v +share/yosys/lattice/cells_sim_nexus.v +share/yosys/lattice/cells_sim_xo2.v +share/yosys/lattice/cells_sim_xo3.v +share/yosys/lattice/cells_sim_xo3d.v +share/yosys/lattice/common_sim.vh +share/yosys/lattice/dsp_map_18x18.v +share/yosys/lattice/dsp_map_nexus.v +share/yosys/lattice/latches_map.v +share/yosys/lattice/lrams_map_nexus.v +share/yosys/lattice/lrams_nexus.txt +share/yosys/lattice/lutrams_map_nexus.v +share/yosys/lattice/lutrams_map_trellis.v +share/yosys/lattice/lutrams_nexus.txt +share/yosys/lattice/lutrams_trellis.txt +share/yosys/lattice/parse_init.vh +share/yosys/microchip/ +share/yosys/microchip/LSRAM.txt +share/yosys/microchip/LSRAM_map.v +share/yosys/microchip/arith_map.v +share/yosys/microchip/brams_defs.vh +share/yosys/microchip/cells_map.v +share/yosys/microchip/cells_sim.v +share/yosys/microchip/polarfire_dsp_map.v +share/yosys/microchip/uSRAM.txt +share/yosys/microchip/uSRAM_map.v +share/yosys/mul2dsp.v +share/yosys/nanoxplore/ +share/yosys/nanoxplore/arith_map.v +share/yosys/nanoxplore/brams.txt +share/yosys/nanoxplore/brams_init.vh +share/yosys/nanoxplore/brams_map.v +share/yosys/nanoxplore/cells_bb.v +share/yosys/nanoxplore/cells_bb_l.v +share/yosys/nanoxplore/cells_bb_m.v +share/yosys/nanoxplore/cells_bb_u.v +share/yosys/nanoxplore/cells_map.v +share/yosys/nanoxplore/cells_sim.v +share/yosys/nanoxplore/cells_sim_l.v +share/yosys/nanoxplore/cells_sim_m.v +share/yosys/nanoxplore/cells_sim_u.v +share/yosys/nanoxplore/cells_wrap.v +share/yosys/nanoxplore/cells_wrap_l.v +share/yosys/nanoxplore/cells_wrap_m.v +share/yosys/nanoxplore/cells_wrap_u.v +share/yosys/nanoxplore/io_map.v +share/yosys/nanoxplore/latches_map.v +share/yosys/nanoxplore/rf_init.vh +share/yosys/nanoxplore/rf_rams_l.txt +share/yosys/nanoxplore/rf_rams_m.txt +share/yosys/nanoxplore/rf_rams_map_l.v +share/yosys/nanoxplore/rf_rams_map_m.v +share/yosys/nanoxplore/rf_rams_map_u.v +share/yosys/nanoxplore/rf_rams_u.txt +share/yosys/nexus/ +share/yosys/nexus/cells_sim.v +share/yosys/nexus/cells_xtra.v +share/yosys/nexus/parse_init.vh +share/yosys/pmux2mux.v +share/yosys/python3/ +share/yosys/python3/smtio.py +share/yosys/python3/ywio.py +share/yosys/quicklogic/ +share/yosys/quicklogic/common/ +share/yosys/quicklogic/common/cells_sim.v +share/yosys/quicklogic/pp3/ +share/yosys/quicklogic/pp3/abc9_map.v +share/yosys/quicklogic/pp3/abc9_model.v +share/yosys/quicklogic/pp3/abc9_unmap.v +share/yosys/quicklogic/pp3/cells_map.v +share/yosys/quicklogic/pp3/cells_sim.v +share/yosys/quicklogic/pp3/ffs_map.v +share/yosys/quicklogic/pp3/latches_map.v +share/yosys/quicklogic/pp3/lut_map.v +share/yosys/quicklogic/qlf_k6n10f/ +share/yosys/quicklogic/qlf_k6n10f/TDP18K_FIFO.v +share/yosys/quicklogic/qlf_k6n10f/arith_map.v +share/yosys/quicklogic/qlf_k6n10f/bram_types_sim.v +share/yosys/quicklogic/qlf_k6n10f/brams_map.v +share/yosys/quicklogic/qlf_k6n10f/brams_sim.v +share/yosys/quicklogic/qlf_k6n10f/cells_sim.v +share/yosys/quicklogic/qlf_k6n10f/dsp_final_map.v +share/yosys/quicklogic/qlf_k6n10f/dsp_map.v +share/yosys/quicklogic/qlf_k6n10f/dsp_sim.v +share/yosys/quicklogic/qlf_k6n10f/ffs_map.v +share/yosys/quicklogic/qlf_k6n10f/libmap_brams.txt +share/yosys/quicklogic/qlf_k6n10f/libmap_brams_map.v +share/yosys/quicklogic/qlf_k6n10f/sram1024x18_mem.v +share/yosys/quicklogic/qlf_k6n10f/ufifo_ctl.v +share/yosys/sdc/ +share/yosys/sdc/graph-stubs.sdc +share/yosys/sf2/ +share/yosys/sf2/arith_map.v +share/yosys/sf2/cells_map.v +share/yosys/sf2/cells_sim.v +share/yosys/simcells.v +share/yosys/simlib.v +share/yosys/smtmap.v +share/yosys/techmap.v +share/yosys/xilinx/ +share/yosys/xilinx/abc9_model.v +share/yosys/xilinx/arith_map.v +share/yosys/xilinx/brams_defs.vh +share/yosys/xilinx/brams_xc2v.txt +share/yosys/xilinx/brams_xc2v_map.v +share/yosys/xilinx/brams_xc3sda.txt +share/yosys/xilinx/brams_xc3sda_map.v +share/yosys/xilinx/brams_xc4v.txt +share/yosys/xilinx/brams_xc4v_map.v +share/yosys/xilinx/brams_xc5v_map.v +share/yosys/xilinx/brams_xc6v_map.v +share/yosys/xilinx/brams_xcu_map.v +share/yosys/xilinx/brams_xcv.txt +share/yosys/xilinx/brams_xcv_map.v +share/yosys/xilinx/cells_map.v +share/yosys/xilinx/cells_sim.v +share/yosys/xilinx/cells_xtra.v +share/yosys/xilinx/ff_map.v +share/yosys/xilinx/lut_map.v +share/yosys/xilinx/lutrams_xc5v.txt +share/yosys/xilinx/lutrams_xc5v_map.v +share/yosys/xilinx/lutrams_xcu.txt +share/yosys/xilinx/lutrams_xcv.txt +share/yosys/xilinx/lutrams_xcv_map.v +share/yosys/xilinx/mux_map.v +share/yosys/xilinx/urams.txt +share/yosys/xilinx/urams_map.v +share/yosys/xilinx/xc3s_mult_map.v +share/yosys/xilinx/xc3sda_dsp_map.v +share/yosys/xilinx/xc4v_dsp_map.v +share/yosys/xilinx/xc5v_dsp_map.v +share/yosys/xilinx/xc6s_dsp_map.v +share/yosys/xilinx/xc7_dsp_map.v +share/yosys/xilinx/xcu_dsp_map.v diff --git a/cad/yosys-takeover/pkg/README b/cad/yosys-takeover/pkg/README new file mode 100644 index 00000000000..58af3a83bb1 --- /dev/null +++ b/cad/yosys-takeover/pkg/README @@ -0,0 +1,23 @@ ++------------------------------------------------------------------------------- +| Running ${PKGSTEM} on OpenBSD ++------------------------------------------------------------------------------- + +High RAM consumption +==================== + +Synthesizing FPGAs is a memory intensive task. Even relatively small designs +might lead to errors such as + + libc++abi: terminating due to uncaught exception of type std::bad_alloc + Abort trap (core dumped) + +In this case, editing /etc/login.conf(5), to increase the parameters + + default:\ + datasize-max=8192M:\ + datasize-cur=8192M + +helps. Obviously, it is required to log off and on again, before it has any +effect on re-running YoSys. + +

2026-06-13 21:07 Thomas Dettbarn:
New port 4/4: cad_yosys-takeover-0.66pl20260612 (Better name needed)