This is a framework for RTL synthesis tools. It currently has extensive 
Verilog-2005 support and provides a basic set of synthesis algorithms for 
various application domains.

Yosys can be adapted to perform any synthesis job by combining the existing 
passes (algorithms) using synthesis scripts and adding additional passes as 
needed by extending the yosys C++ code base.

Yosys is free software licensed under the ISC license (a GPL compatible 
license that is similar in terms to the MIT license or the 2-clause BSD 
license).

Third-party software distributed alongside this software is licensed under 
compatible licenses. Please refer to abc and libs subdirectories for their 
license terms.
