From: Brad Smith Subject: Re: emulators/qemu: backport i386 fix and add OpenBSD/powerpc64 support To: ports@openbsd.org Date: Sun, 14 Jun 2026 19:17:51 -0400 On 2026-06-11 6:45 a.m., Stuart Henderson wrote: > On 2026/06/11 11:35, Kirill A. Korinsky wrote: >> Brad, ports@, >> >> I'd like to backport two patches to qemu-11.0.1: >> >> 1. Fix for regression for i386 support, which was discussed here: >> https://marc.info/?t=178082576900001&r=1&w=2 >> >> 2. Fix for powerpc64 target which allows run OpenBSD/powerpc64 from >> https://marc.info/?t=178097923600001&r=1&w=2 >> >> Bonus: I catch that it needs py-setuptools as BUILD_DEPENDS. >> >> Ok? >> >> Index: Makefile >> =================================================================== >> RCS file: /cvs/ports/emulators/qemu/Makefile,v >> diff -u -p -r1.262 Makefile >> --- Makefile 29 May 2026 15:55:47 -0000 1.262 >> +++ Makefile 11 Jun 2026 09:32:16 -0000 >> @@ -7,6 +7,7 @@ COMMENT-main= multi system emulator >> COMMENT-ga= QEMU guest agent >> >> VERSION= 11.0.1 >> +REVISION= 0 > I think you only need to bump REVISION-main, this shouldn't affect -ga. Yup. OK with that. >> DISTNAME= qemu-${VERSION} >> CATEGORIES= emulators >> SITES= https://download.qemu.org/ >> @@ -39,6 +40,7 @@ MODPY_RUNDEP= No >> BUILD_DEPENDS= devel/gettext,-tools \ >> devel/meson \ >> devel/ninja \ >> + devel/py-setuptools \ >> shells/bash \ >> sysutils/py-distlib \ >> textproc/py-sphinx \ >> Index: patches/patch-hw_ppc_pnv_psi_c >> =================================================================== >> RCS file: patches/patch-hw_ppc_pnv_psi_c >> diff -N patches/patch-hw_ppc_pnv_psi_c >> --- /dev/null 1 Jan 1970 00:00:00 -0000 >> +++ patches/patch-hw_ppc_pnv_psi_c 11 Jun 2026 09:32:16 -0000 >> @@ -0,0 +1,39 @@ >> +https://marc.info/?l=qemu-devel&m=178097910779871&w=2 >> + >> +Index: hw/ppc/pnv_psi.c >> +--- hw/ppc/pnv_psi.c.orig >> ++++ hw/ppc/pnv_psi.c >> +@@ -688,6 +688,8 @@ static uint64_t pnv_psi_p9_mmio_read(void *opaque, hwa >> + case PSIHB9_ESB_CI_BASE: >> + case PSIHB9_ESB_NOTIF_ADDR: >> + case PSIHB9_IVT_OFFSET: >> ++ case PSIHB9_IRQ_LEVEL: >> ++ case PSIHB9_IRQ_STAT: >> + val = psi->regs[reg]; >> + break; >> + default: >> +@@ -817,18 +819,15 @@ static const MemoryRegionOps pnv_psi_p9_xscom_ops = { >> + static void pnv_psi_power9_set_irq(void *opaque, int irq, int state) >> + { >> + PnvPsi *psi = opaque; >> +- uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)]; >> ++ uint64_t irq_bit = PPC_BIT(irq); >> + >> +- if (irq_method & PSIHB9_IRQ_METHOD) { >> +- qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n"); >> +- return; >> +- } >> +- >> +- /* Update LSI levels */ >> ++ /* Update LSI levels and pending status */ >> + if (state) { >> +- psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq); >> ++ psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= irq_bit; >> ++ psi->regs[PSIHB_REG(PSIHB9_IRQ_STAT)] |= irq_bit; >> + } else { >> +- psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq); >> ++ psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~irq_bit; >> ++ psi->regs[PSIHB_REG(PSIHB9_IRQ_STAT)] &= ~irq_bit; >> + } >> + >> + qemu_set_irq(psi->qirqs[irq], state); >> Index: patches/patch-target_i386_tcg_emit_c_inc >> =================================================================== >> RCS file: patches/patch-target_i386_tcg_emit_c_inc >> diff -N patches/patch-target_i386_tcg_emit_c_inc >> --- /dev/null 1 Jan 1970 00:00:00 -0000 >> +++ patches/patch-target_i386_tcg_emit_c_inc 11 Jun 2026 09:32:16 -0000 >> @@ -0,0 +1,22 @@ >> +https://marc.info/?l=qemu-devel&m=178096490372293&w=2 >> + >> +Index: target/i386/tcg/emit.c.inc >> +--- target/i386/tcg/emit.c.inc.orig >> ++++ target/i386/tcg/emit.c.inc >> +@@ -3768,10 +3768,13 @@ static void gen_SAHF(DisasContext *s, X86DecodedInsn * >> + return gen_illegal_opcode(s); >> + } >> + tcg_gen_shri_tl(s->T0, cpu_regs[R_EAX], 8); >> +- gen_neg_setcc(s, JCC_O << 1, cpu_cc_src); >> +- tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O); >> ++ gen_neg_setcc(s, JCC_O << 1, s->T1); >> ++ tcg_gen_andi_tl(s->T1, s->T1, CC_O); >> + tcg_gen_andi_tl(s->T0, s->T0, CC_S | CC_Z | CC_A | CC_P | CC_C); >> +- tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, s->T0); >> ++ tcg_gen_or_tl(s->T0, s->T0, s->T1); >> ++ >> ++ decode->cc_src = s->T0; >> ++ decode->cc_op = CC_OP_EFLAGS; >> + } >> + >> + static void gen_SALC(DisasContext *s, X86DecodedInsn *decode) >> Index: patches/patch-target_ppc_mmu-book3s-v3_c >> =================================================================== >> RCS file: patches/patch-target_ppc_mmu-book3s-v3_c >> diff -N patches/patch-target_ppc_mmu-book3s-v3_c >> --- /dev/null 1 Jan 1970 00:00:00 -0000 >> +++ patches/patch-target_ppc_mmu-book3s-v3_c 11 Jun 2026 09:32:16 -0000 >> @@ -0,0 +1,58 @@ >> +https://marc.info/?l=qemu-devel&m=178097910779871&w=2 >> + >> +Index: target/ppc/mmu-book3s-v3.c >> +--- target/ppc/mmu-book3s-v3.c.orig >> ++++ target/ppc/mmu-book3s-v3.c >> +@@ -23,19 +23,21 @@ >> + #include "mmu-hash64.h" >> + #include "mmu-book3s-v3.h" >> + >> +-bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t *entry) >> ++static bool ppc64_v3_get_pate_from_size(PowerPCCPU *cpu, target_ulong lpid, >> ++ ppc_v3_pate_t *entry, >> ++ uint64_t table_size) >> + { >> + uint64_t patb = cpu->env.spr[SPR_PTCR] & PTCR_PATB; >> +- uint64_t pats = cpu->env.spr[SPR_PTCR] & PTCR_PATS; >> ++ uint64_t entries; >> + >> + /* Check if partition table is properly aligned */ >> +- if (patb & MAKE_64BIT_MASK(0, pats + 12)) { >> ++ if (patb & (table_size - 1)) { >> + return false; >> + } >> + >> + /* Calculate number of entries */ >> +- pats = 1ull << (pats + 12 - 4); >> +- if (pats <= lpid) { >> ++ entries = table_size / sizeof(*entry); >> ++ if (entries <= lpid) { >> + return false; >> + } >> + >> +@@ -44,4 +46,25 @@ bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong l >> + entry->dw0 = ldq_phys(CPU(cpu)->as, patb); >> + entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8); >> + return true; >> ++} >> ++ >> ++bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t *entry) >> ++{ >> ++ uint64_t pats = cpu->env.spr[SPR_PTCR] & PTCR_PATS; >> ++ >> ++ /* >> ++ * Keep the existing ISA v3.0 PATS interpretation first. OpenBSD/powernv >> ++ * uses the PATSIZE value it writes to PTCR as one exponent smaller, and it >> ++ * only needs that interpretation for the bare metal LPID 0 table. >> ++ */ >> ++ if (ppc64_v3_get_pate_from_size(cpu, lpid, entry, 1ull << (pats + 12))) { >> ++ return true; >> ++ } >> ++ >> ++ if (lpid == 0) { >> ++ return ppc64_v3_get_pate_from_size(cpu, lpid, entry, >> ++ 1ull << (pats + 11)); >> ++ } >> ++ >> ++ return false; >> + } >> >> >> -- >> wbr, Kirill >>